Monday, November 15, 2010

DFx for Assembly

DFx for Assembly

Complete a manufacturing risk assessment before you build!  Reduce production asset time, potential production delays, and quality issues before they happen.  That’s the key to Dfx.  There is no doubt that the speed at which technology is advancing is one of the main challenges for assemblers.  Components are getting smaller, boards are tighter and more dense, and PCBs are more complex.  How can the assembler anticipate potential issues before going into production?  Will you source the right parts from the full AVL to ensure their packages are not different?  Will the parts in the Bill of Material fit on the footprint well, or will you need to adjust the stencil?  What is the component mix.  Is there Manufacturing Risk of the design received from the customer?
In addition, efficient and effective communication between Design and Manufacturing is critical for success.
 (http://communities.mentor.com)

PCB Engineer vacancy

Hiteleca Engineering is an US-Indonesian joint venture Electronics Engineering and Assembly company. We are a growing engineering oriented company that provides the PCB layout design services and Front End Assembly Engineering to the electronics industries in the USA.

We are looking for an experienced, self motivated and honest

Electronics Engineer / PCB Designer

Job Requirements:
  • Minimum 3 years experience in Electronics Manufacturing / Design field.
  • University degree in Electrical Engineering
  • Understanding of Bill of Materials (BOM)
  • Understanding of SMT (Surface Mount Technology) process
  • Familiar with Electronics Component
  • Understanding of PCB Layout
  • Experience with Cadence Allegro or Mentor PADS is a plus
  • Good command of English
Job Descriptions:
  • Create and maintain Electronics component library
  • Review Bill of Materials
  • Create Manufacturing Process Instructions
  • Perform Design for Manufacturability
  • Schematic review
  • PCB Layout
Electronics Drafter / CAD Librarian
Job Requirements:
  • Minimum Diploma III / Degree in Mechanical or Electrical Engineering
  • Familiar with Electronics components
  • Understanding AutoCAD or other CAD System
  • Excellent Microsoft Excel skill
  • rganized and diligent
  • Good Command of English (writing)
Job Descriptions:
  • Create and maintain electronics component library
  • Internet search for component datasheet
  • Perform Design for Manufacturability
  • Review Bill of Materials
  • Review and compare parametric data
If you met the requirements above, please submit your resume to : rfid.jobs@gmail.com

Saturday, November 13, 2010

eif_cadence-583003-Error translating input record in Cadence Allegro

***********ERROR      22Dec2006.142228.713  2252  7.6.0R3(96) Windows XP
Cadence Interface - File films_AAV3362520_A65_00.out has wrong header
Status raised : module - G:/s76/eif/eif_cadence.c, line - 2984
Status raised : module - G:/s76/eif/eif_cadence.c, line - 2740
Status raised : module - G:/s76/eif/eif_cadence.c, line - 2486
***********INTERNAL   22Dec2006.142228.713  2252  7.6.0R3(96) Windows XP
(ind_list != NULL && ind_list->magic == IND_LIST_MAGIC) at G:/s76/gen/gen_sort.c 1265
Status raised : module - G:/s76/eif/eif_cadence.c, line - 2062
Status raised : module - G:/s76/eif/eif_main.c, line - 617
Status raised : module - G:/s76/translators/brd2odb/brd2odb.c, line - 393


The workaround of eif_cadence-583003-Error translating input record error while exporting brd file to odb++ is modified the Decimal places:3 to 5, and modified Artwork format from Gerber 4x00 to Gerber RS274X.

Glossary of Stencil Terms

Glossary of Stencil Terms

  • Aperture: An opening in the stencil that corresponds to a land area on the circuit board to be printed.
  • Aperture Design Rules: A set or procedure of rules with recommendations for aperture reductions and mofications in order to optimize stencil design and printing performance.
  • Stencil Overview
  • Aperture Reductions and Modifications: Changes in size or shape of stencil apertures in relation to the corresponding landing pad. These changes are designed to improve paste deposition and yield.
  • Aperture Shape: The outline of the opening in the stencil, as viewed from squeegee side. Common shapes include rectangles, squares, rounds, ovals and "home plate."
  • Aperture Size: Refers to the width and length dimensions of the opening in the stencil.
  • Aspect Ratio: The aspect ratio is the ratio of the aperture opening to the stencil thickness. For chemically etched stencils, this should be greater than 1.5, for laser cut stencils it should be greater than 1.2 and for electroformed stencils which has the best solder paste release characteristics this should be greater than 1.1. Anything less than these recommended ratios will cause the solder paste to stick into the apertures during release as the retaining force of the paste in the aperture will be stronger than the force pulling the paste out of the aperture. See formula.
  • Area Ratio: The relationship between the surface of the aperture and the inside surface of the aperture walls in the stencil. The major difference with Aspect Ratio is that Area Ratio is more suitable to shapes such as circles. Since solder paste has a certain adhesion force, it will stick to the walls of the aperture and to the pad. A ratio of 0.66 pad-to-wall is considered acceptable in our industry ( for example a 13.5 mil circle in a 5 mil thick stencil). See formula.
  • CAD/CAM: Computer Aided Design and Computer Aided Manufacturing is the general terminology for file types used for computerized design and manufacturing.
  • Chem-Etch: This is the least sophisticated manufacturing method for making stencils. It is a photosensitive process that creates a negative photo image on the metal foil. A double sided chemical etching process is used to etch the material away in selected areas resulting in the apertures. The apertures are very smooth but have an hour-glass cross section.
  • Electroform: The most sophisticated manufacturing technique for stencils. It is a photosensitive process with a positive image used to make a disposable mandril. Electrolitic plating is used for this additive process where we actually grow the stencil around the apertures. The apertures are very smooth with a very fine resolution.
  • Fiducial: A mark in the artwork that is etched in the stencil along with the apertures. It is used by the machine vision system to align the stencil to the PCB and to verify artwork orientation and location. Fiducials can be fully-etched or half-etched either on the top (squeegee side) or bottom (board side) of the stencil. Sometimes the fiducials are filled with black epoxy to provide contrast between the stencil and the fiducial for visual systems. "Global" fiducials are located outside the aperture footprint while "local" fiducials are placed within the image itself, usually in close proximity to an integrated circuit.
  • File Layer: Describes the layer of the PCB that the Gerber information represents. The solder paste layer is a 1:1 reflection of the component lands on the board.
  • Frame Mount: Stencils are usually secured to an aluminum frame with a tightly-stretched mesh border. Alternatively, a stencil can have mounting holes etched along the perimeter for temporary mounting on a universal sized frame, such as the ALPHA® TETRA™ frame or competing frameless systems. The user requires typically one frame per printer and buys foils only with the stencil image made in the foil. This foil is then tensioned into the re-usable frame.
  • Frame Size: The size of the frame for mounting stencils is determined by the screen printer model. The smaller cast-aluminum frames are usually specified by the inside dimension (ID), e.g., 12 x 17 or 20 x 20 inches. Tubular aluminum frames are usually specified by the outside dimensions (OD), e.g., 29 x 29 inches.
  • Gasketing: The degree to which a stencil aperture contacts and "seals" against a landing pad. Good gasketing decreases solder "squeeze balls" during printing, that can result in random solder balling and bridging.
  • Gerber Data: Standardized PCB design language and operating commands which ultimately define the slope and location of apertures in a stencil plate.
  • Land: The conductive area on a PCB to which components or separate circuits are attached. Also refered to as pads.
  • Laser Cut: The most popular manufacturing technique for current stencil technology. The CAD/CAM file is used to directly generate a CNC-file that drives the X-Y driven laser head. The laser will cut the perimeters of the apertures, resulting in tapered apertures. The wall structure is rougher than the other techniques due to the ‘melting’ effect of the leaser beam.
  • ODB++: is the most intelligent CAD/CAM data exchange format available today, capturing all CAD/EDA, assembly and PCB fabrication knowledge in one single, unified database. Originally developed by Valor Computerized Systems for use in its own PCB CAD/CAM systems, Genesis 2000, Enterprise 3000 and Trilogy 5000, ODB++ have already become widely accepted as the de facto industry standard, providing unprecedented power to PCB design, fabrication and assembly, with the flexibility to expand as required. In parallel, ODB++ is providing the technological basis for a formal IPC standard
  • Step and Repeat: Repeating a single Gerber file over two or more areas of the same stencil plate. PCB's are arranged on "break away" panels often referred to as 2 Up, 4 Up, etc. . . . Information on the center-to-center dimensions is essential to prevent misregistration of panel to stencil.
  • Step Down/Up: Reduction of stencil thickness in specific areas of a stencil on either the top or bottom side(s). Step UP refers to an area higher/thicker than the majority of the stencil, Step DOWN refers to an area lower/thinner than the majority of the stencil. Stepping is used to control paste deposits on PCB's having both standard pitch and fine pitch components. It is also used for creating an underside cavity to accommodate surface circuitry, vias or other low profile surface components in order to optimize stencil gasketing.
  • Trapezoidal Opening: The cross-sectional angle of the stencil aperture with the larger opening on the bottom side of the stencil and the smaller opening on the top side. This geometry improves solder paste deposition onto the PCB. The laser-cutting and electroforming processes provide trapezoidal openings, whereas, chemically-etched stencils must be etched from both sides of the stencil with a photoresist on the bottom side of the stencil which has slightly larger apertures than the top side photoresist (hour glass).
  • COMMONLY USED FORMULAS:
    Formula 1
    Formula 2
    Formula 3
    Formula 4

Stencil Technology and Design Guidelines for Print Performance

Stencil Technology and Design Guidelines for Print Performance

Circuits Assembly, March, 2001 by William E. Coleman

Three major performance issues exist for solder paste printing. First, the aperture size (width and length of the aperture) and stencil foil thickness determine the potential volume of solder paste applied to the printed circuit board (PCB) or substrate. The second issue is the ability of the solder paste to release from the stencil aperture walls. The third issue is positional accuracy of exactly where the solder brick is printed onto the PCB or substrate.
As the squeegee blade travels across the stencil during the print cycle, solder paste fills the stencil apertures. The paste then releases to the pads on the board during the board/stencil separation cycle. Ideally, 100 percent of the paste that filled the aperture during the print process releases from the aperture walls and attaches to the pads on the board, forming a complete solder brick. The ability of the paste to release from the inner aperture walls depends primarily on three major factors:
* the area ratio/aspect ratio for stencil design
* the aperture side wall geometry
* the aperture wall smoothness.
The first factor is aperture design-related while the other two factors are stencil technology-related. The area ratio is the area beneath the aperture opening divided by the area of the inside aperture wall; area ratio = [(LXW)/(2(L W)T)]. Historically, the aspect ratio is the width of the aperture divided by the thickness of the stencil; aspect ratio = W/T. The generally accepted design guideline for acceptable paste release is [greater than]0.66 for the area ratio and [greater than]1.5 for the aspect ratio.

The aspect ratio is really a one-dimensional simplification of the area ratio. When the length (L) is much larger than the width (W), the area ratio is the same as the aspect ratio. When the stencil separates from the substrate, paste release encounters a competing process: Will it transfer to the pad on the substrate or will it stick to the side aperture walls? When the area of the pad is greater than two-thirds of the area of the inside aperture wall, the paste will probably achieve 80 percent or better paste release.
A laser-cut stencil that is electropolished definitely has smoother inside aperture walls than a non-electropolished laser-cut stencil. Therefore, the former will release a higher percentage of paste than the latter at a given area ratio. Likewise, an electroformed stencil with mirror-type aperture wall finish will release even a higher percentage of paste at the same area ratio. For aspect ratios that approach 1.5 and area ratios that approach 0.66, some stencil technologies are better suited than others to achieve higher percentages of paste release.
The aspect ratio and the area ratio are important considerations when designing stencil apertures. For example, a 20-mil pitch quad flat pack (QFP) with an aperture design of 10 mil X 60 mil in a 5-mil stencil has an aspect ratio of 2.0 and an area ratio of 0.86. Good print performance can be expected with this design using a good quality laser stencil.
However, consider a 20-mil micro ball grid array (microBGA) with a 10-mil aperture in a 5-mil-thick stencil. Because the aperture is round or is a square with rounded corners, the area ratio is the deciding factor. In this case, the area ratio is 0.5, which is well below the recommended value of 0.66. The aperture design can be changed by reducing the stencil thickness or increasing the aperture size, or a stencil technology can be chosen that gives better paste release at this area ratio.
Stencil Technologies
Basically, five stencil technologies are being used in the industry: laser-cut, electroformed, chemical etched, plastic and hybrid. Hybrid is a combination of chemetch and laser-cut. Chem-etch is very useful for step stencils and hybrid stencils.
Laser-cut process
Laser-cut is a subtractive process. The Gerber data is translated into a CNC-type language that the laser understands. The aperture is cut out by moving the laser head only, moving the table holding the stencil only or a combination of each. The laser beam enters inside the aperture boundary and traverses to the perimeter where it completely cuts the aperture out of the metal, one aperture at a time. The smoothness of cut depends on many parameters, including cut speed, beam spot size, laser power and beam focus. The typical beam spot size is about 1.25 mils. The laser can cut very accurate aperture sizes over a wide range of size and shape requirements.
As with chem-etch, the laser-cut aperture size must be adjusted to the post-processing treatment employed because aperture size change will occur during this process. Figure 1 shows scanning electron microscope (SEM) pictures of laser-cut apertures with no electropolish, with electropolish and with electropolish followed with nickel plating.
Electroform process
Electroformed stencils are made by an additive process as opposed to the subtractive process used for chem-etch and laser-cut. A nickel bath containing nickel ions and a nickel hardening additive is used to electroplate onto a substrate called a mandrel. However, photoresist is first applied to the mandrel. The resist is exposed and developed, forming photoresist pillars anywhere an aperture must be in the stencil. Nickel is electroplated out of the bath one ion at a time until the desired foil thickness is achieved. Then, the nickel foil is removed from the mandrel, creating the completed stencil.

(http://findarticles.com/p/articles/mi_hb5118/is_3_12/ai_n28828421/)

Tuesday, November 9, 2010

PCB DFM Checks – Fixing Problems Before They Get to Manufacturing

Before any PCB design goes to even the prototyping stage, the engineers at Electronic Interconnect (EI) subject that design to a number of reviews and checks to make sure that the PCB that the customer requests can actually be built. Quite often, designers will submit the artwork for a PCB that is superb in concept, but may not be compatible with the limits of the manufacturing process, explains Shehryar Abbasi of EI’s Engineering Department. Beyond that, a PCB design may also create issues for the assembly stage, such as a lack of solder mask between component leads that might cause bridging and shorts during the soldering process, when components are attached to the bare board. All of these things must be looked at, Abbasi says, in light of DFM: Design for Manufacturability and DRC: Design Rule Check principles and limitations. “We don’t run files ‘as is’; every board that we make initially goes through a comprehensive DFM check” Abbasi says.Design for Manufacturability, or DFM, is essentially a set of rules that facilitate the smooth manufacturing of PCBs, to ensure that the artwork, drilling/routing, and v-scoring data are compatible with the tolerances of fabrication. Normally, most of the Gerber data that EI receives has some feature that needs to be corrected or reported back to PCB Designer.
DFM checking is a service that EI provides to all customers ordering PCBs, and is intended to identify and solve problems before they end up creating headaches downstream. DFM at EI includes the following checks:
Soldermask clearances - distance to keep mask away from solderable areas;
Soldermask bridges - mask between SMDs to prevent solder bridging during later assembly;
Trace/Pad Widths & Spacing - minimum spacing and trace widths, trace width tolerances allowed;
Copper finish - to determine how much artwork compensation needs to be done for chemical processes.
These are the primary checks, but there is a lot more, all having to do with the fabricator’s ability to make the PCB in accordance with the customer’s requirements. These checks include Drill to Pad Ratio, Inner Layer Copper clearances, Silkscreen Line Widths, Silkscreen clearances from Solderable Pads, Drill Diameter tolerances, Aspect ratio (ratio of smallest drill to thickness of board), Board Outline's spacing to Copper/Drill features, and Board Outline's tolerances for Routing and V-Scoring.
“We go through their proposed board, layer by layer, to make sure that we can actually manufacture their PCB and to make sure that it is within our technology range” Abbasi says. “The checks that we do include minimum trace width and minimum trace spacing, as well as other tolerances. If there are issues that are not easily solvable, then we contact the customer’s designer, or design engineer, to let them know that there are issues that will impact our ability to manufacture their product. We also check the solder mask for clearances, etc., we will adjust as needed, or contact the customer once again to solve the problem.”
EI checks everything with regard to drilling, including drill sizes, and aspect ratio of drill size to board thickness. “For example, if you have a 10-mil via on a 125-mil thick board, we may not be able to drill such a small diameter via on such a thick board, that’s a reason for us to contact the customer. We also check for annular rings and pad to drill ratios, especially keeping in mind what classification the customer wants us to build to, for example a Class II, or a Class III product.”
In terms of assembly-related issues, EI has been noticing that more and more customers are requesting the presence of mask between finer pitch SMT pads. This is because IC footprints are constantly shrinking, and in many cases there is no mask between adjacent pads. This causes shorts when solder flows over to an adjacent pad during the assembly process because there is no mask there to inhibit that flow. In that instance, EI’s design engineers check to see if it is possible to apply mask within the space given during the fabrication of the PCB.
Bare Board, first runMany designers – indeed most – are not familiar with the many constraints of the PCB fabrication process, and as a result it is imperative that EI’s engineers work in close collaboration with the customer’s designer so that they can ultimately produce a working, robust PCB that will also lend itself to the board assembly process and yield a robust product. “It does not benefit anyone if we are able to fabricate a board that is full of problems for the assembly process, such as a high rate of soldering defects that cannot be reduced, excessive rework, and problems like that” Abbasi adds.
The customer’s designer needs to be aware of EI’s capabilities. “For example, if a designer asks for a 1-mil silkscreen line width, he isn’t aware that it is something for which we simply cannot manufacture a screen. So they need to be aware of the limitations of the PCB fabrication process.” Most of the time, EI engineers will be able to change or modify the design; otherwise, the designer has to make the necessary design modifications.
For most of these problems or issues, the ongoing miniaturization of electronic assemblies is the culprit. “The technology is shrinking; we’re doing as much as possible to catch things in the front end before they go to manufacturing” Abbasi says.
Design Rule Check (DRC) and DFM checks can be initiated at the CAD Design stage, during PCB Layout. However, from Abbasi’s experience, EI has seen that most PCB designers either do not know what manufacturing tolerances they should set, or they leave it for the PCB fabricator to fix and/or report back. DFM tolerances differ from manufacturer to manufacturer, but the engineers at EI know their shop's tolerances from Artwork to Drilling/Routing, and Scoring.
For more information: Electronic Interconnect (EI) is a professional printed circuit board manufacturer located in the Chicago area, and manufacturing printed circuit boards in the U.S. since 1985. EI serves design engineers and contract assemblers, providing all types of PCBs from single-sided to complex multilayer boards from prototype through production

http://www.electronicsproductionworld.com/articleView~idArticle~72955_85752271682010.html

Improving fabrication yields by design: the PCB designer is the architect for improved PCB yields.(DFM)

A major requirement in improving board fabrication yields is doing it right the first time, because once the PCB fabrication process is complete there is really no way to go back to fix major mistakes. In some cases you can mitigate design issues during the PCB assembly process, but during PCB fabrication, once layers are laminated and the holes are drilled, you cannot easily undo the process to make corrections.
Therefore, to improve fabrication yields during and after design layout, it's critical to follow the detailed fabrication notes and drawings, specifically calling out every item that requires any kind of explanation. This includes stack up data, layer construction information, material call outs, as well as drill charts specifying hole counts and symbols, whether drill holes are plated, and any similar information.
Notes and drawings must not have sketchy or ambiguous information, nor should they lead the PCB fabricator to make "guesstimates" about some of the directions. Fabrication notes and drawings must have clear-cut and precise information in their instructions--assumptions are not allowed. If questions arise, the OEM customer should be consulted, and the OEM should resolve any uncertainties.
A good rule of thumb is to engage the fabrication house during PCB layout/design stage. After the designer creates the stack up for impedance control, it's a good idea to get it verified before the files are released to the fab house. Conversely, the fab house can play a reciprocal role by providing the designer with recommendations and suggestions for boosting yields. For example, a fab house may recommend material changes for a specific application that are better suited to increasing yields than those a designer specifies.

(http://www.entrepreneur.com/tradejournals/article/177870884.html)